1. Field of the Invention
The present invention is directed to the field of semiconductor processing, and, more particularly, to a method of forming conductive interconnections on an integrated circuit device.
2. Description of the Related Art
There is a constant drive to reduce the size, or scale, of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of millions of transistors formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections.
Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of alternating layers of conductive lines and conductive plugs formed in layers of insulating materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.
By way of background, an illustrative transistor 10 that may be included in such an integrated circuit device is shown in FIG. 1. The transistor 10 is generally comprised of a gate insulation layer 14, a gate conductor 16, and a plurality of source/drain regions 18 formed in a semiconducting substrate 12. The gate insulation layer 14 may be formed from a variety of materials, such as silicon dioxide. The gate conductor 16 may also be formed from a variety of materials, such as polysilicon. The source and drain regions 18 may be formed by one or more ion implantation processes in which a dopant material is implanted into the substrate 12.
In one illustrative process flow, a first insulation layer 26 is formed above the transistor 10, and a plurality of openings 24 are formed in the first insulation layer 26. Thereafter, the openings 24 are filled with a conductive material, such as a metal, to form conductive plugs 22. In the illustrative transistor 10 shown in FIG. 1, the conductive plugs 22 are electrically coupled to the source and drain regions 18 of the transistor 10. Within the semiconductor industry, the conductive plugs 22 may be referred to as either contacts or vias. In general, conductive plugs that are coupled to regions of a transistor, e.g., source/drain regions, are referred to as contacts. Conductive plugs that serve other functions, such as connecting two different layers of conductive lines, are known as vias. However, different terminology may be employed within the industry to distinguish conductive plugs on this basis. Thus, as used herein, the term conductive plugs should be understood to include both contacts and vias.
Thereafter, a second insulation layer 32 may be formed above the first insulation layer 26. Multiple openings 30 may be formed in the second insulation layer 32, and the openings 30 may thereafter be filled with a conductive material to form conductive lines 28. Although only a single level of conductive plugs and a single level of conductive lines are depicted in FIG. 1, there may be multiple levels of plugs and lines interleaved with one another. This interconnected network of plugs and lines allows electrical signals to propagate throughout the integrated circuit device. The techniques used for forming the various components depicted in FIG. 1 are known to those skilled in the art and will not be repeated here in any detail.
The conductive plugs 22 and conductive lines 28 may be of any size or configuration, they may be formed by any of a variety of techniques, and they may be comprised of any of a variety of conductive materials. Traditionally, the conductive plugs 22 depicted in FIG. 1 have a circular cross-section, i.e., the plug is essentially a cylinder of material. However, the plug 22 can be made into any of a variety of shapes, e.g., square, rectangular, etc. Further, the insulation layers 26, 32 may be comprised of any insulating material, such as silicon dioxide or a low-k dielectric. Typically, the insulating layer 26 is formed by depositing the layer 26, and thereafter, subjecting it to a planarization operation, such as a chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d) operation, so as to produce an essentially planar surface 27. Next, the plurality of openings 24 are formed in the insulation layer 26 by performing a photolithographic process and one or more etching processes, e.g., an anisotropic plasma etching process.
Thereafter, a layer (not shown) of the appropriate conductive material, e.g., a metal, may be blanket-deposited, or otherwise formed, over the transistor 10, thereby filling the openings 24 formed in the first insulation layer 26. The metal layer (not shown) may thereafter be subjected to a CMP process to remove the excess material, thereby leaving the conductive plugs 22 in the openings 24.
Next, the insulation layer 32 is formed above the insulation layer 26, and the plurality of openings 30 may be defined in the insulation layer 32 through use of traditional photolithography and etching processes. Thereafter, the conductive line 28 is formed in the opening 30 in the insulation layer 32. As with the plug 22, the conductive line 28 may be formed in any of a variety of shapes, using any of a variety of known techniques for forming such lines, and may be comprised of a variety of materials. For example, the conductive line 28 may be comprised of tungsten, aluminum etc. That is, the conductive lines 28 may be formed by depositing or growing a layer of the appropriate conductive material in the openings 30.
As stated previously, the packing density of transistors formed on an integrated circuit device continues to increase. In turn, this necessitates that the conductive lines and plugs used to interconnect these various transistors also be reduced in size. FIGS. 2A-2C are enlarged, cross-sectional views that depict at least one problem encountered with forming conductive interconnections in modern integrated circuit devices. More particularly, as shown in FIG. 2A, a conductive line 46 is formed in an opening 45 formed in an insulation layer 40. Thereafter, an insulation layer 42 is formed above the insulation layer 40 and the conductive line 46, and an opening 44 is formed therein. A conductive plug 48 (see FIG. 2C) will ultimately be formed in the opening 44 in the insulation layer 42.
The opening 44 has an aspect ratio that is defined by the ratio of the depth xe2x80x9cdxe2x80x9d of the opening 44 as compared to the width xe2x80x9cwxe2x80x9d of the opening 44. As this aspect ratio increases, the act of filling the opening 44 with a conductive material becomes increasingly difficult. In modem semiconductor devices, the aspect ratio of a typical opening for a conductive plug may range from approximately 1-7. Moreover, there is continual pressure to increase the aspect ratio of these openings due to the requirement that transistors be densely packed in modem integrated circuit devices.
As shown in FIG. 2B, a layer of conductive material 41 is formed above the insulation layer 42 and in the opening 44. Due to the relatively high aspect ratio of the opening 41, the layer of conductive material 44 xe2x80x9cpinches offxe2x80x9d in a region indicated by arrow 43 and, in some instances, can result in the formation of a void 47 in the completed plug 48, as shown in FIGS. 2B-2C. This problem is commonly known in the industry by a variety of terms such as xe2x80x9cbreadloafingxe2x80x9d or xe2x80x9ckeyholing.xe2x80x9d
The xe2x80x9cbreadloafingxe2x80x9d or xe2x80x9ckeyholingxe2x80x9d situation depicted in FIGS. 2A-2C is believed to be caused by a variety of factors. For example, in the case when the plug 48 is comprised of tungsten, the tungsten material tends to form more rapidly on the sidewalls 44A of the opening 44, as compared to a bottom surface 44B due to the larger surface area of the sidewalls 44A as compared to the bottom 44B, and because the tungsten starts to form on the sidewalls 44A prior to forming on the bottom 44B. Another reason for this problem occurring is that, as the tungsten is formed in the opening 44 using traditional prior art process flows, the grain size of the tungsten material tends to increase as the tungsten continues to be formed in the opening 44. This continual increase in the grain size of the tungsten material also at least assists in creating the xe2x80x9cbreadloafingxe2x80x9d problems described above.
Although the void 45 is depicted in FIGS. 2B-2C, it may not be formed in all situations. Even when the void 45 is not formed, there may nevertheless be a large seam formed in the conductive plug 48 when it is completed. Additionally, although not depicted in FIGS. 2B-2C, a layer of barrier material, e.g, a barrier layer, may be formed in the opening 44 prior to forming the layer of conductive material 41 in the opening 44. This barrier layer may be a dual layer combination of titanium and titanium nitride. Thereafter, as indicated in FIG. 2C, a planarization operation may be performed on the structure depicted in FIG. 2B to result in a conductive plug 48.
In one illustrative prior art process flow, the layer of conductive material 41 is comprised of tungsten, and it may be formed by forming silicon seed atoms in the opening 44, and thereafter performing one or more tungsten growing processes to form the tungsten material in the opening 44. More particularly, the process may involve initially nucleating silicon seed atoms by using a given quantity of silane gas. Thereafter, by means of an exchange reaction using tungsten hexafluoride (WF6), the tungsten atoms in the tungsten hexafluoride seek out the previously nucleated silicon atoms and essentially replace them. The process then continues with growing additional tungsten material in the opening until such time as the process is deemed completed. During this process flow, as the tungsten material is being formed in the opening 44, the grain size of the tungsten material tends to continually increase as more and more tungsten is formed in the opening. That is, the tungsten material initially formed by replacing the nucleated silicon seed atoms has a smaller grain size than subsequently formed tungsten material. This process continues as the tungsten material is formed in the opening 44.
The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.
The present invention is directed to a method of forming conductive interconnections on an integrated circuit device. In one illustrative embodiment, the method comprises forming an opening in a layer of insulation material, forming a first plurality of silicon seed atoms in the opening, and performing a first tungsten growing process to form tungsten material in the opening. The method further comprises forming a second plurality of silicon seed atoms in the opening above at least a portion of the tungsten material formed during the first tungsten growing process, and performing at least one additional tungsten growing process after forming the second plurality of silicon seed atoms to further form tungsten material in the opening.